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. 4. VHDL
4. VHDL

     , , ( ) . (Hardware Description Language), , . , , . , , , , . : AHDL, VHDL, VerilogHDL, Abel . , , .

     (AHDL, Abel) , , .

     VHDL, 19831987 . , .

    VHDL .

     (structural description), .

     (data-flow description), , . , .

    , , (behavioral description), , . .

     , , , .

     VHDL .

     (entity) , . , , , , , , , , . . , , , . , . , . (design hierarchy).

     , , : . (entity declaration) .

     (architecture body). , , (configuration declaration).

     VHDL , , , . (package declaration). , , (package body).

     , VHDL, : , , , . VHDL, " " (design unit). , , : . . . , (design file). (design library) (library unit). . VHDL (). , , . .

     (data object) . , VHDL , . , , . VHDL , : , , .

     . . .

     . , , , . . . . . , , , "+", "-" integer. VHDL; , Max, . , . . , (True False) . , , . : , if. , , , . , .

     VHDL.

     . , n- "d", "load" "clk". n "" "oclk". "e" . 11041 .

     VHDL 1.

1

library ieee;
use ieee.std_logic_1164.all;

entity Serial is
   port  (
         clk   : in STD_LOGIC;
		 load  : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 d     : in STD_LOGIC_vector (3 downto 0);
		 oclk  : out STD_LOGIC;
		 o     : out STD_LOGIC;
		 e     : out STD_LOGIC
		 );
end;

architecture behavioral of Serial is
   type t1 is range 0 to 4;
       signal s : STD_LOGIC_vector (2 downto 0);
   signal i : t1;
   
begin

process (clk)
   begin
   if reset = "1" then
		  i <=0;
   else
	 if (clk'event and clk='1') then
			if (i = 0 and load = "1") then
					s(2 downto 0) <= d(3 downto 1);
					o <= d(0);
					i <= 4;
			end if;
			if (i > 1) then
					 o <= s(0);
					 s(1 downto 0) <= s(2 downto 1);
			         i <= i - 1;
			end if;
			if (i = 1) then
					  e <= "1";
					  i <= 0;
			else
					   e <= "0";
			end if;
			end if;
		 end if;
		 if i >0 then
		             oclk <= not clk;
		 else
		             oclk <= "0";
	     end if;
		 
end process;

end behavioral;

     "clk" d[3..1] s[2..0]. d[0] "o". "oclk" . "i" , "e". "o" , s[2..0].

     OrCAD 9.0.

     ( 2).

2


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_serial is end test_serial;
architecture tastbench of test_serial is
component serial
 port  (
   clk : in std_logic;
   load : in std_logic;
   reset : in std_logic;
   d : in std_logic_vector(3 downto 0);
   oclk : out std_logic;
   o : out std_logic;
   e : out std_logic
     );
end component;

signal clk : std_logic;
signal load : std_logic := "0";
signal reset : std_logic;
signal d : std_logic_vector(3 downto 0);
signal oclk : std_logic;
signal o : std_logic;
signal e : std_logic;
begin
      process begin
	          for i in 0 to 50 loop
			          clk <= "0"; wait for 5 ns;
					  clk <= "1"; wait for 5 ns;
			  end loop;
	  end process;
	  process begin
	          reset <= "1"; wait for 10 ns;
			  reset <= "0" ;
			  load <= "1";
			  d <= «1010»;wait for 10 ns;
			  load <= "0";
			  d <= «0000»;wait for 500 ns;
	  end process;
dut : serial port map (
    clk => clk,
	load => load,
	reset => reset,
	d => d,
	oclk => oclk,
	o => o,
	e => e
	  );
end testbench;

     . 1.

1

     -.

     -

yn = A0xn + A1xn-1 + A2xn-2 + ...,

     yn n; xn ; Ai i- .

     VHDL , 3.

3


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity f is
port (
       din: in std_logic_vector(7 downto 0);
	   sout:out std_logic_vector(15 downto 0);
	   r: in std_logic;
	   c: in std_logic
	   );
end f;

architecture behavior of is

constant h00 : std_logic_vector(7 downto 0) := «00000000»;
constant h01 : std_logic_vector(7 downto 0) := «00000001»;
constant h02 : std_logic_vector(7 downto 0) := «00000100»;
constant h03 : std_logic_vector(7 downto 0) := «00001111»;
constant h04 : std_logic_vector(7 downto 0) := «00100100»;
constant h05 : std_logic_vector(7 downto 0) := «01000010»;
constant h06 : std_logic_vector(7 downto 0) := «01100100»;
constant h07 : std_logic_vector(7 downto 0) := «01111100»;
constant h08 : std_logic_vector(7 downto 0) := «01111111»;
constant h09 : std_logic_vector(7 downto 0) := «01101010»;
constant h10 : std_logic_vector(7 downto 0) := «01000010»;
constant h11 : std_logic_vector(7 downto 0) := «00100011»;
constant h12 : std_logic_vector(7 downto 0) := «11101100»;
constant h13 : std_logic_vector(7 downto 0) := «11010110»;
constant h14 : std_logic_vector(7 downto 0) := «11010101»;
constant h15 : std_logic_vector(7 downto 0) := «11100011»;
constant h16 : std_logic_vector(7 downto 0) := «11110111»;
constant h17 : std_logic_vector(7 downto 0) := «00001010»;
constant h18 : std_logic_vector(7 downto 0) := «00010100»;
constant h19 : std_logic_vector(7 downto 0) := «00010011»;
constant h20 : std_logic_vector(7 downto 0) := «00001100»;
constant h21 : std_logic_vector(7 downto 0) := «00000010»;
constant h22 : std_logic_vector(7 downto 0) := «11111000»;
constant h23 : std_logic_vector(7 downto 0) := «11110101»;

signal x00, x01, x02, x03,x04, x05, x06, x07,
        x08, x09, x10, x11, x12, x13, x14, x15,
		x16, x17, x18, x19, x20, x21,
		x22, x23 : std_logic_vector(7 downto 0);
signal m00, m01, m02, m03, m04, m05, m06, m07,
        m08, m09, m10, m11, m12, m13, m14, m15,
		m16, m17, m18, m19, m20, m21,
		m22, m23 : std_logic_vector(15 downto 0); 
		
begin
m00 <= (signed(x00)*signd(h00));
m01 <= (signed(x01)*signd(h01));
m02 <= (signed(x02)*signd(h02));
m03 <= (signed(x03)*signd(h03));
m04 <= (signed(x04)*signd(h04));
m05 <= (signed(x05)*signd(h05));
m06 <= (signed(x06)*signd(h06));
m07 <= (signed(x07)*signd(h07));
m08 <= (signed(x08)*signd(h08));
m09 <= (signed(x09)*signd(h09));
m10 <= (signed(x10)*signd(h10));
m11 <= (signed(x11)*signd(h11));
m12 <= (signed(x12)*signd(h12));
m13 <= (signed(x13)*signd(h13));
m14 <= (signed(x14)*signd(h14));
m15 <= (signed(x15)*signd(h15));
m16 <= (signed(x16)*signd(h16));
m17 <= (signed(x17)*signd(h17));
m18 <= (signed(x18)*signd(h18));
m19 <= (signed(x19)*signd(h19));
m20 <= (signed(x20)*signd(h20));
m21 <= (signed(x21)*signd(h21));
m22 <= (signed(x22)*signd(h22));
m23 <= (signed(x23)*signd(h23));

sout <= (signed(m00)+signed(m01)+signed(m02)+signed(m03)
           +signed(m04)+signed(m05)+signed(m06)+signed(m07)
		   +signed(m08)+signed(m09)+signed(m10)+signed(m11)
		   +signed(m12)+signed(m13)+signed(m14)+signed(m15)
		   +signed(m16)+signed(m17)+signed(m18)+signed(m19)
		   +signed(m20)+signed(m21)+signed(m22)+signed(m23));
		   
process(c,r)
       begin
	   if r='1' then
	          x00 <= (others => "0");
			  x01 <= (others => "0");
			  x02 <= (others => "0");
			  x03 <= (others => "0");
			  x04 <= (others => "0");
			  x05 <= (others => "0");
			  x06 <= (others => "0");
			  x07 <= (others => "0");
			  x08 <= (others => "0");
			  x09 <= (others => "0");
			  x10 <= (others => "0");
			  x11 <= (others => "0");
			  x12 <= (others => "0");
			  x13 <= (others => "0");
			  x14 <= (others => "0");
			  x15 <= (others => "0");
			  x16 <= (others => "0");
			  x17 <= (others => "0");
			  x18 <= (others => "0");
			  x19 <= (others => "0");
			  x20 <= (others => "0");
			  x21 <= (others => "0");
			  x22 <= (others => "0");
			  x23 <= (others => "0");
	   elsif (c'event andc='1') then
	          x00(7 downto 0) <= din(7 downto 0);
			  x01(7 downto 0) <= x00(7 downto 0);
			  x02(7 downto 0) <= x01(7 downto 0);
			  x03(7 downto 0) <= x02(7 downto 0);
			  x04(7 downto 0) <= x03(7 downto 0);
			  x05(7 downto 0) <= x04(7 downto 0);
			  x06(7 downto 0) <= x05(7 downto 0);
			  x07(7 downto 0) <= x06(7 downto 0);
			  x08(7 downto 0) <= x07(7 downto 0);
			  x09(7 downto 0) <= x08(7 downto 0);
			  x10(7 downto 0) <= x09(7 downto 0);
			  x11(7 downto 0) <= x10(7 downto 0);
			  x12(7 downto 0) <= x11(7 downto 0);
			  x13(7 downto 0) <= x12(7 downto 0);
			  x14(7 downto 0) <= x13(7 downto 0);
			  x15(7 downto 0) <= x14(7 downto 0);
			  x16(7 downto 0) <= x15(7 downto 0);
			  x17(7 downto 0) <= x16(7 downto 0);
			  x18(7 downto 0) <= x17(7 downto 0);
			  x19(7 downto 0) <= x18(7 downto 0);
			  x20(7 downto 0) <= x19(7 downto 0);
			  x21(7 downto 0) <= x20(7 downto 0);
			  x22(7 downto 0) <= x21(7 downto 0);
			  x23(7 downto 0) <= x22(7 downto 0);
	  end if;
	  end process;
end behavior;

     din[7..0] "c".

     x0 - x23 , 24 . h0 h23 .

     , 4.

4

-Test bench shell

library ieee;
use ieee.std_logic_1164.all;

entity test_f is end test_f;

architecture testbench of test_f is

component f
 port (
   din : in std_logic_vecor(7 downto 0);
   sout : out std_logic_vector(15 downto 0);
   r: in std_logic;
   c : in std_logic
    );
end component;

signal din : std_logic_vector(7 downto 0);
signal sout : std_logic_vector(15 downto 0);
signal r : std_logic;
signal c : std_logic;

begin

      process begin
	          for i in 0 to 50 loop
			         c <= "0"; wait for 5 ns;
					 c <= "1"; wait for 5 ns;
			  end loop;
	  end process;
	  
	  process begin
	         r <= "1"; wait for 10 ns;
			 r <= "0";
			 din <= «00000001»; wait for 10 ns;
			 din <= «00000000»; wait for 500 ns;
	  end process;
	  
dut : f port map (
    din => din,
	sout => sout,
	r => r,
	c => c
	  );
	  
end testbench;

     d-. .

     . 2.

2

     AHDL ALTERA.

. (095) 263-6736
E-mail: steshenk@sm.bmstu.ru






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